Amon Relayed a Request for a 100-Billion-Parameter Phone. The Arithmetic Has Two Walls.

On 8 October, Alex Heath’s Sources podcast published an interview with Qualcomm’s chief executive, Cristiano Amon. On 11 October a financial news site pulled out one line, and it has been circulating as “Qualcomm says phones will run 100-billion-parameter models by 2028.” The line is closer to a customer request than a roadmap. I have not heard the audio. The wording below comes from Stocktwits’ write-up of the episode, which quotes Amon saying that some AI companies are telling Qualcomm they need the ability to run “at least a 100 billion parameter model” in a phone by 2028, and which adds that those companies want the model running continuously. The show page’s own highlights give the same two numbers and say the AI would be running all the time. They do not give a chip, a memory configuration or a date on which Qualcomm commits to anything.

So the claim to test is narrower than the headline. Can a phone-class memory system plausibly serve a 100-billion-parameter model, and could it do so all the time? I can’t settle that, and neither can Amon’s sentence. But the arithmetic is short enough to do by hand, and it shows which assumptions the request is quietly making.

The first wall is room, not speed

Start with the part that has nothing to do with how fast the chip is. Weights occupy bytes: parameters times bits, divided by eight. A 100-billion-parameter model at 8 bits is 100 GB. At 4 bits it is 50 GB. At 2 bits, 25 GB. That is before the cache of past tokens the model attends to, before activations, and before the operating system takes its share.

The chip whose specifications I could read is the Snapdragon 8 Elite Gen 5. Its product brief (undated; the chip launched in September 2025) lists LPDDR5X memory “up to 5300MHz” and a memory density “up to 24GB”. That is the ceiling the chip supports, not what a phone ships with, and not what an app gets. A trade report on the Gen 6 parts, dated 22 September, lists “LPDDR5x/LPDDR6” at the same 5300 MHz and 24 GB maximum, and says only the Extreme version runs mixture-of-experts models of 30 billion parameters locally. I found no Qualcomm document for the Gen 6, so I have worked from the Gen 5. In a September preprint on running large mixture-of-experts models on phones, Li and colleagues list the memory of their test devices. The OnePlus 15, which carries the Gen 5, has 16 GB of which 11.52 GB was available to inference. The OnePlus 13, on the previous-generation Snapdragon 8 Elite, has 24 GB of which 18.23 GB was available.

Phone memory available versus the weights of a 100-billion-parameter model Horizontal bars in gigabytes. Phone side: OnePlus 15, usable RAM: 11.52 GB; OnePlus 13, usable RAM: 18.23 GB; Gen 5 spec ceiling: 24 GB. Model side, weights only: 8-bit weights: 100 GB; 4-bit weights: 50 GB; 2-bit weights: 25 GB. Even the 2-bit model exceeds the usable RAM of the 24 GB phone. GIGABYTES · PHONE RAM VS 100B-PARAMETER WEIGHTS · QUALCOMM, LI ET AL., 2026 WHAT THE PHONE OFFERS OnePlus 15, usable RAM Snapdragon 8 Elite Gen 5, of 16 GB 11.52 GB — OnePlus 15, usable RAM 11.52 GB OnePlus 13, usable RAM previous-generation chip, of 24 GB 18.23 GB — OnePlus 13, usable RAM 18.23 GB Gen 5 spec ceiling LPDDR5X, up to 24 GB 24 GB — Gen 5 spec ceiling 24 GB WHAT A 100B MODEL NEEDS 8-bit weights 100 GB — 8-bit weights 100 GB 4-bit weights 50 GB — 4-bit weights 50 GB 2-bit weights 25 GB — 2-bit weights 25 GB Weights only; no KV cache, activations or operating system. Bytes = parameters × bits ÷ 8.
Usable RAM was measured on two retail phones; the model sizes are my arithmetic. Nothing here depends on how fast the chip is.

Even the most aggressive precision on the table does not fit. A 2-bit, 100-billion-parameter model is about 25 GB, which is above the 18.23 GB that the 24 GB phone actually offered. The 4-bit version is roughly 2.7 times that figure. If Amon’s customers mean a model resident in memory, then somebody has to ship a lot more of it, and neither the brief nor the interview coverage I found says anyone has promised to.

The same brief lists the Gen 5 NPU as supporting INT2, INT4, INT8, INT16 and FP8 and FP16 precisions, mixed precision included. Two-bit arithmetic is on the hardware today. What the sheet cannot tell you is whether a 100-billion-parameter model survives being squeezed to two bits with its usefulness intact, and I found no 2026 paper that answers that.

The second wall is the bus

Now suppose the room exists. Generating one token at batch size one means reading, in effect, every weight that participates in that token. I made this argument in September in the piece on small models on phones: decoding is limited by how fast bytes arrive, and the NPU’s trillions of operations a second mostly sit waiting. The ceiling is bandwidth divided by bytes read per token.

The Gen 5’s bandwidth is not on the brief. I derived it: 5300 MHz at double data rate is 10.6 gigabits per pin, and a third-party spec table lists a 64-bit memory bus, which gives 84.8 GB/s. Treat that as a peak, and as my arithmetic on someone else’s bus width. Real phones deliver less: the BigMoMo authors cite up to 78 GB/s for LPDDR5X.

At that peak, a dense 100-billion-parameter model at 4 bits caps out at 1.70 tokens per second, because each token reads 50 GB. At 2 bits it is 3.39. That is a token every 0.6 seconds at best, before the attention cache and the operating system take their cut. It is a ceiling. Measured rates come in under it.

Sparse models change this number a great deal, and they are the realistic route. A mixture-of-experts model with 100 billion parameters in total but about 10 billion active per token reads only the active experts: 5 GB at 4 bits, for a ceiling of 16.96 tokens per second. With 3 billion active it is 1.5 GB and 56.5 tokens per second. The active-parameter counts are my assumptions, since Amon gave none.

Decoding ceilings for 100-billion-parameter models on a phone, from DRAM and from flash Dumbbell chart on a log scale. Filled dot is the bandwidth ceiling at 84.8 gigabytes per second of DRAM; hollow dot is the ceiling if every active weight is read from flash at 4 gigabytes per second. 100B dense, 4-bit: 1.7 tokens per second from DRAM, 0.08 from flash; 100B dense, 2-bit: 3.39 tokens per second from DRAM, 0.16 from flash; 100B mixture, ~10B active, 4-bit: 16.96 tokens per second from DRAM, 0.80 from flash; 100B mixture, ~3B active, 4-bit: 56.5 tokens per second from DRAM, 2.67 from flash. TOKENS PER SECOND, UPPER BOUND · DRAM (FILLED) VS FLASH (HOLLOW) 0.1 1 10 100 100B dense, 4-bit 50 GB read per token 0.08 tokens/s ceiling if every active weight is read from flash at 4 GB/s 1.7 tokens/s ceiling at 84.8 GB/s DRAM bandwidth 1.70 | 0.08 100B dense, 2-bit 25 GB read per token 0.16 tokens/s ceiling if every active weight is read from flash at 4 GB/s 3.39 tokens/s ceiling at 84.8 GB/s DRAM bandwidth 3.39 | 0.16 100B mixture, ~10B active, 4-bit 5 GB read per token 0.80 tokens/s ceiling if every active weight is read from flash at 4 GB/s 16.96 tokens/s ceiling at 84.8 GB/s DRAM bandwidth 16.96 | 0.80 100B mixture, ~3B active, 4-bit 1.5 GB read per token 2.67 tokens/s ceiling if every active weight is read from flash at 4 GB/s 56.5 tokens/s ceiling at 84.8 GB/s DRAM bandwidth 56.5 | 2.67 upper bound, tokens per second (log scale) Ceiling = bandwidth ÷ bytes per token; ignores KV cache. Right column: DRAM | flash.
Moving from a dense model to a sparse one buys speed, not room. All eight bounds assume the weights are already where the chip can reach them.

But look at what the sparse model did and did not fix. It cut the bytes read per token. It did not cut the bytes that must exist somewhere. A 100-billion-parameter mixture at 4 bits is still 50 GB, and the phone has 11 to 18 GB. The rest lives in flash, and flash is slow. Li and colleagues put typical phone flash at around 4 GB/s, with worse figures for the small scattered reads that expert routing produces. If every active weight came from flash at that rate, the ceilings fall to 0.80 tokens per second at 10 billion active and 2.67 at 3 billion. The hollow dots in the chart use that 4 GB/s with every active weight read from flash. Nobody would run it that way, which is what the research below is for, and it is a best case for flash, since scattered expert reads do worse.

That research is the best evidence on the table, and it is aimed at a smaller target than the request. Li and colleagues’ BigMoMo runtime streams experts from flash, uses speculative decoding to batch their movement, and reports speedups of 4.83 times over on-demand offloading and, averaged over its test set, 1.76 times over the best speculative baseline (the abstract states 1.82, and the paper does not reconcile the two). The averages come from four models of 21 to 30 billion parameters; the paper separately claims support for models up to 80 billion. Those are ratios against other offloading schemes on short-generation benchmarks (128 to 256 output tokens), not a sustained rate for a 100-billion-parameter model. It is real progress on the second wall. It does nothing for the first.

Newer memory is not a way out on paper either. JEDEC published the LPDDR6 standard in July 2025, but the release states no data rates or bandwidth, so I have assumed no gain from it.

“Continuously” is where the physics shows up

The request, as reported, also wants the model running all the time. Here the best direct evidence is on a much smaller model and older phones, so it bounds the question rather than answering it. Tummalapalli and colleagues’ March preprint ran a 1.5-billion-parameter model at 4 bits for 20 warm iterations on a Samsung Galaxy S24 Ultra and an iPhone 16 Pro. The iPhone lost nearly half its throughput within two iterations. The Galaxy hit an OS-enforced GPU frequency floor that, in the authors’ words, terminates inference entirely. A separate October preprint by Geyko and colleagues, on fine-tuning rather than decoding, found that sustained training on an iPhone 17 Pro throttled the phone to about half its initial throughput and that none of the pause schedules they tried recovered it.

Those are one small model, a handful of devices and different workloads. They do not say what a 2028 phone does. They do say that “peak tokens per second” and “all the time” are separate claims, and a ceiling computed from memory bandwidth is blind to heat.

What would have to be true

I’d read the request as three engineering bets stacked together. The model is sparse, with single-digit billions of parameters active. The phone carries much more memory than the 24 GB the current chip is specified for, or a flash path far better than 4 GB/s, or a precision low enough to fit the weights in what is already there. And “continuously” means a small always-on component that wakes the large one, not a 100-billion-parameter model decoding around the clock. Each bet is plausible alone. I found nothing in the interview coverage that says Qualcomm has made any of them.

None of this makes Amon wrong. He was describing what customers are asking for, and a request can be ambitious without being a forecast. The part worth keeping is the unit. When someone says a model of a given size will run on a phone, the questions are how many bytes are read per token, how many bytes have to live in the phone, how fast those bytes arrive, and for how long before the phone throttles. The parameter count answers none of them.

References

  1. Heath, A. (2026). Qualcomm’s CEO on the coming AI phone supercycle. Sources, 8 October 2026.
  2. Stocktwits (2026). Qualcomm CEO Cristiano Amon: AI companies want 100B-parameter models on phones by 2028. 11 October 2026. Secondhand quotation from the Sources episode.
  3. Qualcomm (undated). Snapdragon 8 Elite Gen 5 Mobile Platform product brief. Memory and precision specifications; the 84.8 GB/s peak is my derivation, using a third-party bus width.
  4. Li, M., et al. (2026). BigMoMo: Efficient Inference of Large-Scale MoE with Speculative Decoding on Mobile Devices. arXiv:2609.14643, 13 September 2026.
  5. Tummalapalli, P., et al. (2026). LLM Inference at the Edge: Mobile, NPU, and GPU Performance Efficiency Trade-offs Under Sustained Load. arXiv:2603.23640, 24 March 2026.
  6. Geyko, A., et al. (2026). Fine-Tuning a 3B-Parameter LLM on a Smartphone: Characterizing Sustained Training. arXiv:2610.06325, 5 October 2026.
  7. JEDEC (2025). JEDEC Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance. 9 July 2025.
  8. ITdaily (2026). Qualcomm Snapdragon 8 Elite Gen 6 and Extreme. 22 September 2026. Trade report; specifications not confirmed against a Qualcomm document.